2012-05-25

SRC clears path to 14-nm with directed self-assembly litho

SRC clears path to 14-nm with directed self-assembly litho

PORTLAND, Ore.—A novel self-assembly technique previously demonstrated only in the lab for regular test patterns, has been perfected for creating the irregular patterns necessary to fabricate real semiconductors down to 14-nanometers, according to researchers funded by Semiconductor Research Corp. (SRC).

By solving one of the outstanding lithographic problems facing further scaling—the tiny contact holes that connect semiconductors to their substrate—researchers at Stanford University have demonstrated working circuits at 22-nanometer and a clear path to 14-nanometers, as well as a bee-line on the chemistry developments needed to scale to single digit sizes.

"Others have demonstrated self-assembly of regular patterns," said Philip Wong, lead researcher at Stanford for the SRC-guided research. "But this is the first time that directed self-assembly (DSA) has been successfully applied to create the critical contact holes needed for standard cell libraries on future sub-22-nanometer chips."

The semiconductors fabricated by Wong's group were real working circuits at 22-nanometer, not just test structures, demonstrating that DSA can be used for any irregular pattern required for future logic or memory chips. The group also demonstrated that they could heal imperfections in patterns and maintain high resolutions and ultra-fine features consistently across a wafer.

"At SRC, we view Wong's work as the critical breakthrough needed to pattern contact hole patterns at advanced nodes, which is one of the most difficult problems the industry is facing today," said Bob Havemann, director of nanomanufacturing sciences at SRC (Research Triangle, N.C.). "Wong was also able to achieve the patterning using environmentally green materials, which is another obstacle that needed to be surmounted."

Stanford's technique works by first using standard lithography techniques to pattern the general area where the contact hole will need to be, using features than can be more than twice the size of the final contact holes. For instance, if pair of contact holes been to be spaced 22 nanometers apart, then the template might be used to etch an oblong indentation that is 50 nanometers long. Then, in the second step, a self-assembling block-copolymer is deposited on the wafer, where it only activates within the indented areas. By carefully formulating the two parts of the co-polymer, it self assembles into precisely the placement pattern required to accurately etch closely spaced side-by-side 22 nanometer holes.

"Our current demonstration showed we could etch irregular patterns of 22 nanometer holes," said Linda He Yi, a researcher working on Wong’s team. "But our current copolymer can handle etching holes in patterns as small as 14 nanometers."

The solvents used in the coating and etching process were polyethylene glycol monomethyl ether acetates, which are considered a green alternative to conventional solvents. Other SRC projects underway are aiming to extend the green directed self-assembly technique to single-digit sizes below 10-nanometer, by perfecting different copolymer formulations.

Additional funding for the project was provided by the National Science Foundation.


TAG:Semiconductor 14 nm Nanoscale Microchip Fab EETimes NextGenLog Electronics

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