Business SuVolta and UMC develop low power 28nm process

Business SuVolta and UMC develop low power 28nm process

2013/07/23

UMC and SuVolta are to develop a 28nm process that integrates SuVolta’s Deeply Depleted Channel (DDC) transistor technology into UMC’s 28nm process.

DDC transistor technology reduces leakage power and improve SRAM low-voltage performance.

The companies also announced that the process technology will deliver various options:

A DDC PowerShrink low-power platform option for the ultimate power and performance benefit, where all transistors utilize the DDC technology.

A DDC DesignBoost transistor swap option that works with existing design databases where a subset of transistors are replaced with DDC transistors. Typical applications of this option are replacing the leakier transistors with DDC transistors that could cut leakage, or replacing the SRAM bitcell transistors with DDC transistors to improve performance and lower minimum operating voltage (Vmin)

“By incorporating SuVolta’s advanced technology into our HKMG process, we intend to deliver a 28nm mobile computing process platform to complement our existing Poly-SiON and HKMG technologies,” says UMC’s T.R.Yew.

“Working together, we are developing a process that makes for easy porting of UMC’s customers’ designs,” says Bruce McWilliams, CEO of SuVolta, “SuVolta is advancing future generations of mobile devices by providing the industry with an alternative to more costly and technically challenging process technologies.”

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