Auto IC gains breath new life into car market

Auto IC gains breath new life into car market

GENEVA, Switzerland -- The demise of the automobile has been greatly exaggerated thanks in large part to engineering innovations by automotive electronics companies.

The auto market has been revived through a broad range of engineering innovations from suppliers like STMicroelectronics, based here, along with rivals Freescale Semiconductor and Japan’s Renesas Electronics. Among the innovations either in testing or production are technologies to help to reduce carbon dioxide emissions, improved fuel efficiency and new passenger safety features.

Meanwhile, the self-driving car is no longer a dream and the automobile is becoming, for better or worse, the ultimate mobile communications and entertainment hub.

"The most important trend within the market continues to be the greater integration of infotainment features into vehicles' central head units in the dashboard or front console,” market watcher IHS said in a recent report. Making this possible are both wired and wireless connectivity features such as Bluetooth, Wi-Fi and USB for use in navigation and telematics.

"The future of the automotive is bright," predicted Marco Monti, executive vice president and general manager of ST's automotive product group. "It used to be an object that was considered dangerous, but it is becoming a tool that is having less impact on the environment.” What’s more, the growing number of infotainment features in cars are fast becoming must-haves for consumers.

Electronics have vastly improved auto functionality, Monti added, giving drivers a batch of new sensors ranging from cameras to gyroscopes. The next step will be integrating cars with networks and greater vehicle autonomy. "You can have a car that is behaving independently of your judgment. It is getting to a point where you don't always need to know how the car is working. It just does,” Monti said.

Delivering vehicles crammed with new features while determining consumer preferences in the different regions is now one of the biggest challenges facing auto OEMs, subassembly manufacturers and semiconductor vendors. Regional differences can be huge. Auto OEMs currently sell different models in different regions. The features marketed in each region depend on factors like regulatory requirements and customer preferences. Often, these varying requirements affect vehicle design and the types of components manufacturers purchase from suppliers.

ST, for instance, said it works closely with Chinese auto manufacturers at the system level, making the "direct relationship between the automakers and semiconductor companies stronger in China, for example, than it is in Europe," according to Monti. That’s because Chinese manufacturers want system-level solutions and are glad to invite the suppliers to participate early in the design stage.

As the auto IC market continues to expand and ST and its rivals increase R&D spending, they are gaining more leverage in the market as barriers for entry by new semiconductor vendors grow. One reason is that the average auto OEM designs vehicles five years ahead of market introduction. While the types of electronics used in autos is constantly changing, these lead times create a major hurdle for new IC suppliers seeking new auto design wins.

Moreover, auto makers dealing with more frequent product recalls tend to stick with trusted suppliers.

That means emerging Chinese chip vendors will have a tough time unseating incumbents like ST as long as it can deliver what manufacturers want, when they want it. Hence, the focus of auto electronics competition for the foreseeable future will be among ST, Freescale and Renesas.

Related stories:

Higher gas prices, drive car, auto IC sales

Driving ST's auto IC strategy: Manufacturing line can't stop




TAG:Automotive Electronics STMicroelectronics Freescale Renesas China Auto ICs Auto Recalls

What Intel's 'Me The Musical' leaves out

What Intel's 'Me The Musical' leaves out

NEW YORK – Wow. Talk about alternative reality… or, should I say, revisionist history?

I am talking about Intel’s recently launched ‘Me The Musical’ campaign, which piggy- backs on Facebook.


TAG:Intel Facebook Musical

UMC set to beat TSMC to FinFET process

UMC set to beat TSMC to FinFET process

LONDON – Taiwan's United Microelectronics Corp. (UMC), which has been a struggling number two behind foundry leader Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), could get one over on its long-time rival by being first in production with FinFET process technology.

This is despite the fact that TSMC (Hsinchu, Taiwan) was one of the originators of the FinFET idea more than a decade ago.

UMC (Hsinchu, Taiwan), courtesy of a licensing deal with computing giant IBM, could be in production with a 20-nm FinFET process as soon as in the second-half of 2014; up to a year ahead of the latest disclosed timing from TSMC.

The process UMC has licensed is for FinFETs on bulk silicon rather than on silicon-on-insulator wafers, according to a spokesperson. This makes it easier to introduce quickly after a running a 20-nm bulk CMOS process. Reports suggest that making sure fins are well defined with a rectangular cross section can make a marked difference to performance and that making FinFETs on SOI wafers could produce a further improvement in leakage current performance.

Shih-Wei Sun, CEO of UMC did not demur when it was put to him that UMC was targeting 2014 for the introduction of 20-nm FinFETs, in a conference call to discuss UMC's second quarter financial results.

He added that UMC's first FinFET would be based on the same 20-nm back-end process as a 20-nm planar CMOS. He said most companies were doing this but that some were defining it as a 16- or 14-nm process. He added that this was really a marketing definition. This is in line with an explanation of a two-step 20-nm process given to analysts recently by Eric Meurice, CEO of lithography equipment vendor ASML.

The latest from TSMC is that its first FinFET process will be at 16-nm and that it is due to ramp in the second half of 2015. Although if TSMC is also using its 20-nm back-end for its FinFET process it may have the option to bring forward its timetable for a FinFET process.


Related links and articles:

FinFETs-on-SOI can double battery life, says GSS

ARM, TSMC sign deal to ease FinFET process introduction

ASML outlines a FinFET process 'two-step'

UMC licenses IBM technology for 20-nm FinFETs


TAG:UMC TSMC FinFET IBM ASML semiconductor process

What Intel's 'Me The Musical' leaves out

What Intel's 'Me The Musical' leaves out

NEW YORK – Wow. Talk about alternative reality… or, should I say, revisionist history?

I am talking about Intel’s recently launched ‘Me The Musical’ campaign, which piggy- backs on Facebook.


TAG:Intel Facebook Musical

UMC set to beat TSMC to FinFET process

UMC set to beat TSMC to FinFET process

LONDON – Taiwan's United Microelectronics Corp. (UMC), which has been a struggling number two behind foundry leader Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), could get one over on its long-time rival by being first in production with FinFET process technology.

This is despite the fact that TSMC (Hsinchu, Taiwan) was one of the originators of the FinFET idea more than a decade ago.

UMC (Hsinchu, Taiwan), courtesy of a licensing deal with computing giant IBM, could be in production with a 20-nm FinFET process as soon as in the second-half of 2014; up to a year ahead of the latest disclosed timing from TSMC.

The process UMC has licensed is for FinFETs on bulk silicon rather than on silicon-on-insulator wafers, according to a spokesperson. This makes it easier to introduce quickly after a running a 20-nm bulk CMOS process. Reports suggest that making sure fins are well defined with a rectangular cross section can make a marked difference to performance and that making FinFETs on SOI wafers could produce a further improvement in leakage current performance.

Shih-Wei Sun, CEO of UMC did not demur when it was put to him that UMC was targeting 2014 for the introduction of 20-nm FinFETs, in a conference call to discuss UMC's second quarter financial results.

He added that UMC's first FinFET would be based on the same 20-nm back-end process as a 20-nm planar CMOS. He said most companies were doing this but that some were defining it as a 16- or 14-nm process. He added that this was really a marketing definition. This is in line with an explanation of a two-step 20-nm process given to analysts recently by Eric Meurice, CEO of lithography equipment vendor ASML.

The latest from TSMC is that its first FinFET process will be at 16-nm and that it is due to ramp in the second half of 2015. Although if TSMC is also using its 20-nm back-end for its FinFET process it may have the option to bring forward its timetable for a FinFET process.


Related links and articles:

FinFETs-on-SOI can double battery life, says GSS

ARM, TSMC sign deal to ease FinFET process introduction

ASML outlines a FinFET process 'two-step'

UMC licenses IBM technology for 20-nm FinFETs


TAG:UMC TSMC FinFET IBM ASML semiconductor process

What Intel's 'Me The Musical' leaves out

What Intel's 'Me The Musical' leaves out

NEW YORK – Wow. Talk about alternative reality… or, should I say, revisionist history?

I am talking about Intel’s recently launched ‘Me The Musical’ campaign, which piggy- backs on Facebook.


TAG:Intel Facebook Musical

Reports: Fujitsu is trying to sell its main fab

Reports: Fujitsu is trying to sell its main fab

LONDON – Japan's Fujitsu Ltd. has attempted to open up talks about the sale of its main wafer fab to foundry chip maker Taiwan Semiconductor Manufacturing Co. Ltd., according to reports. The wafer fab in Mie prefecture makes image processing chips and processors for supercomputers.

However, the Wall Street Journal reported that a TSMC spokesperson said the company has no plans to buy any off shore wafer fabs.

An attempt by Fujitsu to sell its fab as a means of going fab-lite or even fabless would follow on from similar move by fellow Japanese company Renesas Electronics Corp.

In May, it was reported that Renesas had tried to persuade TSMC to acquire a system-chip fab in Yamagata as part of a deal to take on increased foundry work for Renesas. But earlier this month Morris Chang, chairman and CEO of TSMC, was reported saying that the foundry had no intention of acquiring the Renesas fab.

In general TSMC's policy is to concentrate wafer fabs together at a couple of sites in Taiwan although it does operate fabs in mainland China and the United States and has a joint venture fab in Singapore.

It was also reported earlier this year that discussions were taking place about Fujitsu, Panasonic and Renesas merging their system-chip operations but nothing has been heard subsequently about such a move.


Related links and articles:

Report: TSMC's Chang says no to buying Renesas fab

SuVolta positions DDC as node life extender

Fujitsu to transfer Iwate fab to Denso

Nikkei: Japanese firms look to merge system IC units


TAG:Fujitsu TSMC Renesas semiconductor fab

UMC set to beat TSMC to FinFET process

UMC set to beat TSMC to FinFET process

LONDON – Taiwan's United Microelectronics Corp. (UMC), which has been a struggling number two behind foundry leader Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), could get one over on its long-time rival by being first in production with FinFET process technology.

This is despite the fact that TSMC (Hsinchu, Taiwan) was one of the originators of the FinFET idea more than a decade ago.

UMC (Hsinchu, Taiwan), courtesy of a licensing deal with computing giant IBM, could be in production with a 20-nm FinFET process as soon as in the second-half of 2014; up to a year ahead of the latest disclosed timing from TSMC.

The process UMC has licensed is for FinFETs on bulk silicon rather than on silicon-on-insulator wafers, according to a spokesperson. This makes it easier to introduce quickly after a running a 20-nm bulk CMOS process. Reports suggest that making sure fins are well defined with a rectangular cross section can make a marked difference to performance and that making FinFETs on SOI wafers could produce a further improvement in leakage current performance.

Shih-Wei Sun, CEO of UMC did not demur when it was put to him that UMC was targeting 2014 for the introduction of 20-nm FinFETs, in a conference call to discuss UMC's second quarter financial results.

He added that UMC's first FinFET would be based on the same 20-nm back-end process as a 20-nm planar CMOS. He said most companies were doing this but that some were defining it as a 16- or 14-nm process. He added that this was really a marketing definition. This is in line with an explanation of a two-step 20-nm process given to analysts recently by Eric Meurice, CEO of lithography equipment vendor ASML.

The latest from TSMC is that its first FinFET process will be at 16-nm and that it is due to ramp in the second half of 2015. Although if TSMC is also using its 20-nm back-end for its FinFET process it may have the option to bring forward its timetable for a FinFET process.


Related links and articles:

FinFETs-on-SOI can double battery life, says GSS

ARM, TSMC sign deal to ease FinFET process introduction

ASML outlines a FinFET process 'two-step'

UMC licenses IBM technology for 20-nm FinFETs


TAG:UMC TSMC FinFET IBM ASML semiconductor process

Reports: Fujitsu is trying to sell its main fab

Reports: Fujitsu is trying to sell its main fab

LONDON – Japan's Fujitsu Ltd. has attempted to open up talks about the sale of its main wafer fab to foundry chip maker Taiwan Semiconductor Manufacturing Co. Ltd., according to reports. The wafer fab in Mie prefecture makes image processing chips and processors for supercomputers.

However, the Wall Street Journal reported that a TSMC spokesperson said the company has no plans to buy any off shore wafer fabs.

An attempt by Fujitsu to sell its fab as a means of going fab-lite or even fabless would follow on from similar move by fellow Japanese company Renesas Electronics Corp.

In May, it was reported that Renesas had tried to persuade TSMC to acquire a system-chip fab in Yamagata as part of a deal to take on increased foundry work for Renesas. But earlier this month Morris Chang, chairman and CEO of TSMC, was reported saying that the foundry had no intention of acquiring the Renesas fab.

In general TSMC's policy is to concentrate wafer fabs together at a couple of sites in Taiwan although it does operate fabs in mainland China and the United States and has a joint venture fab in Singapore.

It was also reported earlier this year that discussions were taking place about Fujitsu, Panasonic and Renesas merging their system-chip operations but nothing has been heard subsequently about such a move.


Related links and articles:

Report: TSMC's Chang says no to buying Renesas fab

SuVolta positions DDC as node life extender

Fujitsu to transfer Iwate fab to Denso

Nikkei: Japanese firms look to merge system IC units


TAG:Fujitsu TSMC Renesas semiconductor fab

Researchers claim smallest semiconductor laser

Researchers claim smallest semiconductor laser

SAN FRANCISCO—Physicists at the University of Texas-Austin say they have developed the world's smallest semiconductor laser in collaboration with colleagues in Taiwan and China.

The researchers say the development is a breakthrough for emerging photonic technology with applications from computing to medicine.

"We have developed a nanolaser device that operates well below the 3-D diffraction limit," said Chih-Kang "Ken" Shih, professor of physics at the University
of Texas, in a statement. "We believe our research could have a large impact on nanoscale technologies."

Shih and his colleagues reported in this week's issue of the journal Science the first operation of a continuous-wave, low-threshold laser below the 3-D diffraction limit. When fired, the nanolaser emits a green light. The laser is too small to be visible to the naked eye.

Researchers say miniaturization of semiconductor lasers is key for the development of faster, smaller and lower energy photon-based technologies, such as ultrafast computer chips; highly sensitive biosensors for detecting, treating and studying disease; and next-generation communication technologies. Such photonic devices could use nanolasers to generate optical signals and transmit information, and have the potential to replace electronic circuits. But the size and performance of photonic devices have been restricted by what's known as the three-dimensional optical diffraction limit, the researchers say.


Physics graduate student Charlotte Sanders' research with Professor Ken Shih helped develop the world's smallest nanolaser.
Photo: Alex Wang, University of Texas-Austin

TAG:Semiconductor Laser Texas Austin

Researchers claim smallest semiconductor laser

Researchers claim smallest semiconductor laser

SAN FRANCISCO—Physicists at the University of Texas-Austin say they have developed the world's smallest semiconductor laser in collaboration with colleagues in Taiwan and China.

The researchers say the development is a breakthrough for emerging photonic technology with applications from computing to medicine.

"We have developed a nanolaser device that operates well below the 3-D diffraction limit," said Chih-Kang "Ken" Shih, professor of physics at the University
of Texas, in a statement. "We believe our research could have a large impact on nanoscale technologies."

Shih and his colleagues reported in this week's issue of the journal Science the first operation of a continuous-wave, low-threshold laser below the 3-D diffraction limit. When fired, the nanolaser emits a green light. The laser is too small to be visible to the naked eye.

Researchers say miniaturization of semiconductor lasers is key for the development of faster, smaller and lower energy photon-based technologies, such as ultrafast computer chips; highly sensitive biosensors for detecting, treating and studying disease; and next-generation communication technologies. Such photonic devices could use nanolasers to generate optical signals and transmit information, and have the potential to replace electronic circuits. But the size and performance of photonic devices have been restricted by what's known as the three-dimensional optical diffraction limit, the researchers say.


Physics graduate student Charlotte Sanders' research with Professor Ken Shih helped develop the world's smallest nanolaser.
Photo: Alex Wang, University of Texas-Austin

TAG:Semiconductor Laser Texas Austin

IEEE forecasts ten-fold data growth by 2015

IEEE forecasts ten-fold data growth by 2015

SAN JOSE – Data traffic is expected to grow ten-fold from 2010 to 2015 and up to 100-fold by 2020, according to a new report from the IEEE’s Ethernet standards group. The assessment aimed to lay a foundation for future work on Ethernet interfaces beyond today’s 40 and 100 Gbit/second standards.

“The various projections show traffic increasing to a factor of ten above the 2010 value from as early as 2013 to as late as 2018,” the report concluded.

The IEEE 802.3 Ethernet Bandwidth Assessment group spent a year developing its 44-page report now online. It culls data from eleven presentations across a variety of technical and geographic markets.

The assessment did not attempt to come to grips with what is seen as one of the thorniest issues facing engineers—finding a path to a cost-effective, next-generation Ethernet standard.

“Whether or not these projections are realized will depend, among other things, on the ability of the Ethernet community to keep the cost per bit falling with time… in such a way that the exponential rise in traffic does not result in unsupportable costs,” the report said.

“The question of whether this increased traffic is serviced by the introduction of new rates above 100 Gbits/s or by increasing numbers of the existing interfaces depends on the ability of the higher rates to provide a sufficiently cost-effective solution,” it added.

Ethernet proponents have engaged in a lively debate over the past two years about whether a 400 Gbit/s or a Terabit rate should be the next target. Traditionally Ethernet standards have marched forward at 10x increments, but some engineers say the terabit goal could overstress technology, resulting in unacceptable costs.

For now the debate remains open. “It is left to future standards activities to determine the best way to service these application spaces,” the report said.

In the meantime, the assessment gathered a wealth of data about expanding bandwidth demands.

Globally, the number of Internet users is forecast to increase from 1.9 billion users in 2010 to three billion in 2015. The biggest group will be 1.3 billion users in Asia/Pacific excluding Japan, followed by 495 million in the Middle east and Africa.

Nearly 15 billion fixed and mobile networked devices and machine-to-machine connections will be online by 2015, the report estimated. The average fixed broadband in 2015 is expected to rise to 28 Mbits/s up from 7 Mbits/s in 2010.

In 2015, 68 percent of all broadband connections are forecast to be at least 5 Mbits/s, 40 percent will be at least 10 Mbits/s, and 3 percent will be at least 100 Mbits/s.

The report forecasted Internet Protocol traffic will jump four-fold from 20 exabytes a month in 2010 to 80 in 2015. Mobile IP data will grow fastest at a 92 percent compound annual rate, but it will only account for 7.7 percent of the total by 2015.

Wired links will grow 24 percent to become 46.1 percent of the total in 2015. Wi-Fi links will grow faster at 39 percent to nudge past wired links become 46.2 percent of IP traffic, the report said.


Wi-Fi is expected to dominate Internet Protocol traffic.
TAG:IEEE Ethernet Bandwidth Assessment Ethernet Data Traffic Networking IEEE

IEEE forecasts ten-fold data growth by 2015

IEEE forecasts ten-fold data growth by 2015

SAN JOSE – Data traffic is expected to grow ten-fold from 2010 to 2015 and up to 100-fold by 2020, according to a new report from the IEEE’s Ethernet standards group. The assessment aimed to lay a foundation for future work on Ethernet interfaces beyond today’s 40 and 100 Gbit/second standards.

“The various projections show traffic increasing to a factor of ten above the 2010 value from as early as 2013 to as late as 2018,” the report concluded.

The IEEE 802.3 Ethernet Bandwidth Assessment group spent a year developing its 44-page report now online. It culls data from eleven presentations across a variety of technical and geographic markets.

The assessment did not attempt to come to grips with what is seen as one of the thorniest issues facing engineers—finding a path to a cost-effective, next-generation Ethernet standard.

“Whether or not these projections are realized will depend, among other things, on the ability of the Ethernet community to keep the cost per bit falling with time… in such a way that the exponential rise in traffic does not result in unsupportable costs,” the report said.

“The question of whether this increased traffic is serviced by the introduction of new rates above 100 Gbits/s or by increasing numbers of the existing interfaces depends on the ability of the higher rates to provide a sufficiently cost-effective solution,” it added.

Ethernet proponents have engaged in a lively debate over the past two years about whether a 400 Gbit/s or a Terabit rate should be the next target. Traditionally Ethernet standards have marched forward at 10x increments, but some engineers say the terabit goal could overstress technology, resulting in unacceptable costs.

For now the debate remains open. “It is left to future standards activities to determine the best way to service these application spaces,” the report said.

In the meantime, the assessment gathered a wealth of data about expanding bandwidth demands.

Globally, the number of Internet users is forecast to increase from 1.9 billion users in 2010 to three billion in 2015. The biggest group will be 1.3 billion users in Asia/Pacific excluding Japan, followed by 495 million in the Middle east and Africa.

Nearly 15 billion fixed and mobile networked devices and machine-to-machine connections will be online by 2015, the report estimated. The average fixed broadband in 2015 is expected to rise to 28 Mbits/s up from 7 Mbits/s in 2010.

In 2015, 68 percent of all broadband connections are forecast to be at least 5 Mbits/s, 40 percent will be at least 10 Mbits/s, and 3 percent will be at least 100 Mbits/s.

The report forecasted Internet Protocol traffic will jump four-fold from 20 exabytes a month in 2010 to 80 in 2015. Mobile IP data will grow fastest at a 92 percent compound annual rate, but it will only account for 7.7 percent of the total by 2015.

Wired links will grow 24 percent to become 46.1 percent of the total in 2015. Wi-Fi links will grow faster at 39 percent to nudge past wired links become 46.2 percent of IP traffic, the report said.


Wi-Fi is expected to dominate Internet Protocol traffic.
TAG:IEEE Ethernet Bandwidth Assessment Ethernet Data Traffic Networking IEEE

ARM adds weight to IoT debate

ARM adds weight to IoT debate

LONDON – Processor intellectual property licensor ARM Holdings plc (Cambridge, England) has invited four U.K. companies to help it form an industry forum to help shape the Internet of Things. The work is being done within the U.K. initially partly to help align it with government initiatives and regulation.

The four companies are Select Innovations Ltd., Neul Ltd., AlertMe.com Ltd. and AquaMW. The forum aims to combat what they describe as the "Internet of Silos" an unconnected world with less value to both consumers and businesses. The forum will drive a blueprint for how technologies associated with the Internet of Things should and could work together to support the 50-billion intelligent devices due to be connected to the Internet by 2020.

Governments are expected to play a key role in defining the regulations that will propel shipments for machine-to-machine communications modules. ARM has an interest in this because it expects to move from having a 30 percent market share of embedded processors in 2011 to about a 50 percent market share in 2016.

The forum's founding members are all involved in technology associated with the Internet of Things, including commercial infrastructure monitoring, energy-saving street lighting, home automation, energy monitoring and low power radio technology for sensors. The first forum meeting is set to take place on Aug. 24 and be chaired by Gary Atkinson, who leads an Internet of Things initiative at ARM.

"In the next five years, over £2.4 billion (about $3.8 billion) will be spent in the U.K. on smart home energy management devices, ranging from smart meters themselves to in-home devices that are connected to them. This is a great example of an Internet of Things application, but is only a fraction of the market that will open up over the next 15 to 20 years," said Atkinson, director of embedded at ARM, in statement. "There are massive opportunities for the U.K. and the industry as a whole in this market, but that requires a common approach to infrastructure and systems to enable the Internet of Things. The UK can lead this thinking and that's why we are establishing a forum to create a blueprint for success.





Related links and articles:

Do machines dream of IoT?

Weightless standard for IoT outlined in book

Former Apple, Google, Facebook engineers launch IoT startup

Libelium lists 50 Internet of Things applications

Murata wants to build from MEMS to Internet of Things

Neul launches 'white-space' smart metering in Cambridge

TAG:Internet of things ARM Neul EnLight IoT M2M semiconductor microcontroler

ARM adds weight to IoT debate

ARM adds weight to IoT debate

LONDON – Processor intellectual property licensor ARM Holdings plc (Cambridge, England) has invited four U.K. companies to help it form an industry forum to help shape the Internet of Things. The work is being done within the U.K. initially partly to help align it with government initiatives and regulation.

The four companies are Select Innovations Ltd., Neul Ltd., AlertMe.com Ltd. and AquaMW. The forum aims to combat what they describe as the "Internet of Silos" an unconnected world with less value to both consumers and businesses. The forum will drive a blueprint for how technologies associated with the Internet of Things should and could work together to support the 50-billion intelligent devices due to be connected to the Internet by 2020.

Governments are expected to play a key role in defining the regulations that will propel shipments for machine-to-machine communications modules. ARM has an interest in this because it expects to move from having a 30 percent market share of embedded processors in 2011 to about a 50 percent market share in 2016.

The forum's founding members are all involved in technology associated with the Internet of Things, including commercial infrastructure monitoring, energy-saving street lighting, home automation, energy monitoring and low power radio technology for sensors. The first forum meeting is set to take place on Aug. 24 and be chaired by Gary Atkinson, who leads an Internet of Things initiative at ARM.

"In the next five years, over £2.4 billion (about $3.8 billion) will be spent in the U.K. on smart home energy management devices, ranging from smart meters themselves to in-home devices that are connected to them. This is a great example of an Internet of Things application, but is only a fraction of the market that will open up over the next 15 to 20 years," said Atkinson, director of embedded at ARM, in statement. "There are massive opportunities for the U.K. and the industry as a whole in this market, but that requires a common approach to infrastructure and systems to enable the Internet of Things. The UK can lead this thinking and that's why we are establishing a forum to create a blueprint for success.





Related links and articles:

Do machines dream of IoT?

Weightless standard for IoT outlined in book

Former Apple, Google, Facebook engineers launch IoT startup

Libelium lists 50 Internet of Things applications

Murata wants to build from MEMS to Internet of Things

Neul launches 'white-space' smart metering in Cambridge

TAG:Internet of things ARM Neul EnLight IoT M2M semiconductor microcontroler

ARM adds weight to IoT debate

ARM adds weight to IoT debate

LONDON – Processor intellectual property licensor ARM Holdings plc (Cambridge, England) has invited four U.K. companies to help it form an industry forum to help shape the Internet of Things. The work is being done within the U.K. initially partly to help align it with government initiatives and regulation.

The four companies are Select Innovations Ltd., Neul Ltd., AlertMe.com Ltd. and AquaMW. The forum aims to combat what they describe as the "Internet of Silos" an unconnected world with less value to both consumers and businesses. The forum will drive a blueprint for how technologies associated with the Internet of Things should and could work together to support the 50-billion intelligent devices due to be connected to the Internet by 2020.

Governments are expected to play a key role in defining the regulations that will propel shipments for machine-to-machine communications modules. ARM has an interest in this because it expects to move from having a 30 percent market share of embedded processors in 2011 to about a 50 percent market share in 2016.

The forum's founding members are all involved in technology associated with the Internet of Things, including commercial infrastructure monitoring, energy-saving street lighting, home automation, energy monitoring and low power radio technology for sensors. The first forum meeting is set to take place on Aug. 24 and be chaired by Gary Atkinson, who leads an Internet of Things initiative at ARM.

"In the next five years, over £2.4 billion (about $3.8 billion) will be spent in the U.K. on smart home energy management devices, ranging from smart meters themselves to in-home devices that are connected to them. This is a great example of an Internet of Things application, but is only a fraction of the market that will open up over the next 15 to 20 years," said Atkinson, director of embedded at ARM, in statement. "There are massive opportunities for the U.K. and the industry as a whole in this market, but that requires a common approach to infrastructure and systems to enable the Internet of Things. The UK can lead this thinking and that's why we are establishing a forum to create a blueprint for success.





Related links and articles:

Do machines dream of IoT?

Weightless standard for IoT outlined in book

Former Apple, Google, Facebook engineers launch IoT startup

Libelium lists 50 Internet of Things applications

Murata wants to build from MEMS to Internet of Things

Neul launches 'white-space' smart metering in Cambridge

TAG:Internet of things ARM Neul EnLight IoT M2M semiconductor microcontroler

Global CO2 emissions up 3% in 2011

Global CO2 emissions up 3% in 2011

PARIS – After a 1-percent decline in 2009 and an unprecedented 5-percent surge in 2010, global emissions of carbon dioxide (CO₂) increased by 3 percent in 2011, to 34 billion tons, according to the annual report 'Trends in global CO₂ emissions" by the European Commission's Joint Research Center (JRC) and the Netherlands Environmental Assessment Agency (PBL).

The 3-percent increase in global CO₂ emissions in 2011 is above the past decade's average annual increase of 2.7 percent, outlined JRC in its latest report. The top emitters contributing to the 34 billion tones of CO₂ emitted globally in 2011 are: China (29 percent), the United States (16 percent), the European Union (11 percent), India (6 percent), the Russian Federation (5 percent) and Japan (4 percent).

In Europe, CO₂ emissions decreased by 3 percent, to 3.8 billion tones, and in the United States by 2 percent, to 5.4 billion tones, in 2011.



TAG:CO2 Emissions European Commission Joint Research Center JRC China India United States

European TSV summit planned

European TSV summit planned

LONDON – SEMI, the international trade association that represents the interests of semiconductor equipment and materials companies, is planning for a 3-D packaging and through silicon via (TSV) meeting to be held in Grenoble, France, on January 22 and 23, 2013.

TSV is a key enabler of 3-D integration of ICs and is one of the areas of focus for European companies who have thought to avoid the expense of monolithic integration.

The event will include both a conference and an exhibition and will support and showcase the capabilities of leading European semiconductor companies in this area, SEMI said.

Participants are expected to demonstrate a full range of 3-D and R&D process from initial prototypes through to high-volume production.

A steering committee has been set up that includes representative of IMEC, CEA-Leti, Fraunhofer-IZM, Suss Microtec, SPTS, AMS and STMicroelectronics.


Related links and articles:

http://www.semi.org/european3DTSVsummit

News articles:

CEA-Leti opens 3-D IC packaging service

Dow Corning and Suss cooperate on making 3-D TSV chips

GlobalFoundries installs gear for 20-nm TSVs

Applied Materials, IME open Singapore 3-D packaging lab

TSMC plans 3-D IC assembly launch early in 2013


TAG:SEMI TSV packaging STMicroelectronics CEA Leti Grenoble

Global CO2 emissions up 3% in 2011

Global CO2 emissions up 3% in 2011

PARIS – After a 1-percent decline in 2009 and an unprecedented 5-percent surge in 2010, global emissions of carbon dioxide (CO₂) increased by 3 percent in 2011, to 34 billion tons, according to the annual report 'Trends in global CO₂ emissions" by the European Commission's Joint Research Center (JRC) and the Netherlands Environmental Assessment Agency (PBL).

The 3-percent increase in global CO₂ emissions in 2011 is above the past decade's average annual increase of 2.7 percent, outlined JRC in its latest report. The top emitters contributing to the 34 billion tones of CO₂ emitted globally in 2011 are: China (29 percent), the United States (16 percent), the European Union (11 percent), India (6 percent), the Russian Federation (5 percent) and Japan (4 percent).

In Europe, CO₂ emissions decreased by 3 percent, to 3.8 billion tones, and in the United States by 2 percent, to 5.4 billion tones, in 2011.



TAG:CO2 Emissions European Commission Joint Research Center JRC China India United States

Global CO2 emissions up 3% in 2011

Global CO2 emissions up 3% in 2011

PARIS – After a 1-percent decline in 2009 and an unprecedented 5-percent surge in 2010, global emissions of carbon dioxide (CO₂) increased by 3 percent in 2011, to 34 billion tons, according to the annual report 'Trends in global CO₂ emissions" by the European Commission's Joint Research Center (JRC) and the Netherlands Environmental Assessment Agency (PBL).

The 3-percent increase in global CO₂ emissions in 2011 is above the past decade's average annual increase of 2.7 percent, outlined JRC in its latest report. The top emitters contributing to the 34 billion tones of CO₂ emitted globally in 2011 are: China (29 percent), the United States (16 percent), the European Union (11 percent), India (6 percent), the Russian Federation (5 percent) and Japan (4 percent).

In Europe, CO₂ emissions decreased by 3 percent, to 3.8 billion tones, and in the United States by 2 percent, to 5.4 billion tones, in 2011.



TAG:CO2 Emissions European Commission Joint Research Center JRC China India United States

European TSV summit planned

European TSV summit planned

LONDON – SEMI, the international trade association that represents the interests of semiconductor equipment and materials companies, is planning for a 3-D packaging and through silicon via (TSV) meeting to be held in Grenoble, France, on January 22 and 23, 2013.

TSV is a key enabler of 3-D integration of ICs and is one of the areas of focus for European companies who have thought to avoid the expense of monolithic integration.

The event will include both a conference and an exhibition and will support and showcase the capabilities of leading European semiconductor companies in this area, SEMI said.

Participants are expected to demonstrate a full range of 3-D and R&D process from initial prototypes through to high-volume production.

A steering committee has been set up that includes representative of IMEC, CEA-Leti, Fraunhofer-IZM, Suss Microtec, SPTS, AMS and STMicroelectronics.


Related links and articles:

http://www.semi.org/european3DTSVsummit

News articles:

CEA-Leti opens 3-D IC packaging service

Dow Corning and Suss cooperate on making 3-D TSV chips

GlobalFoundries installs gear for 20-nm TSVs

Applied Materials, IME open Singapore 3-D packaging lab

TSMC plans 3-D IC assembly launch early in 2013


TAG:SEMI TSV packaging STMicroelectronics CEA Leti Grenoble

European TSV summit planned

European TSV summit planned

LONDON – SEMI, the international trade association that represents the interests of semiconductor equipment and materials companies, is planning for a 3-D packaging and through silicon via (TSV) meeting to be held in Grenoble, France, on January 22 and 23, 2013.

TSV is a key enabler of 3-D integration of ICs and is one of the areas of focus for European companies who have thought to avoid the expense of monolithic integration.

The event will include both a conference and an exhibition and will support and showcase the capabilities of leading European semiconductor companies in this area, SEMI said.

Participants are expected to demonstrate a full range of 3-D and R&D process from initial prototypes through to high-volume production.

A steering committee has been set up that includes representative of IMEC, CEA-Leti, Fraunhofer-IZM, Suss Microtec, SPTS, AMS and STMicroelectronics.


Related links and articles:

http://www.semi.org/european3DTSVsummit

News articles:

CEA-Leti opens 3-D IC packaging service

Dow Corning and Suss cooperate on making 3-D TSV chips

GlobalFoundries installs gear for 20-nm TSVs

Applied Materials, IME open Singapore 3-D packaging lab

TSMC plans 3-D IC assembly launch early in 2013


TAG:SEMI TSV packaging STMicroelectronics CEA Leti Grenoble

ARM, TSMC lead Intel in SoC, says CEO East

ARM, TSMC lead Intel in SoC, says CEO East

LONDON – ARM CEO Warren East is not concerned that Intel Corp. is developing a lead in process technology of the foundries that ARM licensees usually deal with. This is despite the fact that FinFET technology for ARM processors may not be in volume production until the second-half of 2015, according to foundry Taiwan Semiconductor Manufacturing Co. Ltd.

The use of FinFETs, where transistors stick up above the surface, is considered to improve the performance of transistors and reduce leakage current in the off-state. Intel is already manufacturing in volume using in a 22-nm FinFET CMOS process while TSMC is attempting to ramp up planar 28-nm CMOS for is customers.

Nonetheless East told EE Times that ARM and TSMC together lead Intel in the system-on-chip (SoC) technologies where they compete with Intel. "We are concerned about integrated SoC. For SoC Intel is manufacturing using 32-nm high-k metal gate planar CMOS. TSMC is manufacturing using 28-nm high-k metal gate. That doesn't sound like a massive lead to me. If anything you could argue that TSMC is ahead."

East said that Intel's 22-nm FinFET is being used for high-volume PC chips but it would be no easy matter to make an SoC device with an extensive range of peripheral circuits in that process.

Intel has smartphone and tablet computer designs based on its Atom-based 32-nm Medfield processor. Intel is expected to manufacture its Atom low-power processor in the 22-nm FinFET CMOS process in 2013 in an architecture called Silvermont. Merrifield could be a 22-nm FinFET implementation for high-end smartphones.

With regard to the 16-nm FinFET process from TSMC and a 20-nm FinFET process from UMC East said: "It's hard to say exactly when it [FinFET for ARM] is going to arrive."

ARM processor cores are also supported on a 28-nm fully depleted SOI (FDSOI) process developed by STMicroelectronics NV and being transferred to foundry GlobalFoundries Inc. (Milpitas, Calif.) that is expected to subsequently shrink to 20-nm.


Related links and articles:

Intel rewrites Atom road map

Intel tips Medfield specs, Lenovo, Motorola deals

ARM, TSMC sign deal to ease FinFET process introduction

UMC licenses IBM technology for 20-nm FinFETs

ST opens up 28-nm, 20-nm FDSOI with GlobalFoundries

Ecosystem emerges around new mobile chip tech

TAG:Warren East ARM TSMC Intel UMC STMicroelectronics

ARM, TSMC lead Intel in SoC, says CEO East

ARM, TSMC lead Intel in SoC, says CEO East

LONDON – ARM CEO Warren East is not concerned that Intel Corp. is developing a lead in process technology of the foundries that ARM licensees usually deal with. This is despite the fact that FinFET technology for ARM processors may not be in volume production until the second-half of 2015, according to foundry Taiwan Semiconductor Manufacturing Co. Ltd.

The use of FinFETs, where transistors stick up above the surface, is considered to improve the performance of transistors and reduce leakage current in the off-state. Intel is already manufacturing in volume using in a 22-nm FinFET CMOS process while TSMC is attempting to ramp up planar 28-nm CMOS for is customers.

Nonetheless East told EE Times that ARM and TSMC together lead Intel in the system-on-chip (SoC) technologies where they compete with Intel. "We are concerned about integrated SoC. For SoC Intel is manufacturing using 32-nm high-k metal gate planar CMOS. TSMC is manufacturing using 28-nm high-k metal gate. That doesn't sound like a massive lead to me. If anything you could argue that TSMC is ahead."

East said that Intel's 22-nm FinFET is being used for high-volume PC chips but it would be no easy matter to make an SoC device with an extensive range of peripheral circuits in that process.

Intel has smartphone and tablet computer designs based on its Atom-based 32-nm Medfield processor. Intel is expected to manufacture its Atom low-power processor in the 22-nm FinFET CMOS process in 2013 in an architecture called Silvermont. Merrifield could be a 22-nm FinFET implementation for high-end smartphones.

With regard to the 16-nm FinFET process from TSMC and a 20-nm FinFET process from UMC East said: "It's hard to say exactly when it [FinFET for ARM] is going to arrive."

ARM processor cores are also supported on a 28-nm fully depleted SOI (FDSOI) process developed by STMicroelectronics NV and being transferred to foundry GlobalFoundries Inc. (Milpitas, Calif.) that is expected to subsequently shrink to 20-nm.


Related links and articles:

Intel rewrites Atom road map

Intel tips Medfield specs, Lenovo, Motorola deals

ARM, TSMC sign deal to ease FinFET process introduction

UMC licenses IBM technology for 20-nm FinFETs

ST opens up 28-nm, 20-nm FDSOI with GlobalFoundries

Ecosystem emerges around new mobile chip tech

TAG:Warren East ARM TSMC Intel UMC STMicroelectronics

ARM, TSMC lead Intel in SoC, says CEO East

ARM, TSMC lead Intel in SoC, says CEO East

LONDON – ARM CEO Warren East is not concerned that Intel Corp. is developing a lead in process technology of the foundries that ARM licensees usually deal with. This is despite the fact that FinFET technology for ARM processors may not be in volume production until the second-half of 2015, according to foundry Taiwan Semiconductor Manufacturing Co. Ltd.

The use of FinFETs, where transistors stick up above the surface, is considered to improve the performance of transistors and reduce leakage current in the off-state. Intel is already manufacturing in volume using in a 22-nm FinFET CMOS process while TSMC is attempting to ramp up planar 28-nm CMOS for is customers.

Nonetheless East told EE Times that ARM and TSMC together lead Intel in the system-on-chip (SoC) technologies where they compete with Intel. "We are concerned about integrated SoC. For SoC Intel is manufacturing using 32-nm high-k metal gate planar CMOS. TSMC is manufacturing using 28-nm high-k metal gate. That doesn't sound like a massive lead to me. If anything you could argue that TSMC is ahead."

East said that Intel's 22-nm FinFET is being used for high-volume PC chips but it would be no easy matter to make an SoC device with an extensive range of peripheral circuits in that process.

Intel has smartphone and tablet computer designs based on its Atom-based 32-nm Medfield processor. Intel is expected to manufacture its Atom low-power processor in the 22-nm FinFET CMOS process in 2013 in an architecture called Silvermont. Merrifield could be a 22-nm FinFET implementation for high-end smartphones.

With regard to the 16-nm FinFET process from TSMC and a 20-nm FinFET process from UMC East said: "It's hard to say exactly when it [FinFET for ARM] is going to arrive."

ARM processor cores are also supported on a 28-nm fully depleted SOI (FDSOI) process developed by STMicroelectronics NV and being transferred to foundry GlobalFoundries Inc. (Milpitas, Calif.) that is expected to subsequently shrink to 20-nm.


Related links and articles:

Intel rewrites Atom road map

Intel tips Medfield specs, Lenovo, Motorola deals

ARM, TSMC sign deal to ease FinFET process introduction

UMC licenses IBM technology for 20-nm FinFETs

ST opens up 28-nm, 20-nm FDSOI with GlobalFoundries

Ecosystem emerges around new mobile chip tech

TAG:Warren East ARM TSMC Intel UMC STMicroelectronics

金代玉器孤品水圆雕在南京展出

金代玉器孤品水圆雕在南京展出

　　通讯员夏德时报道 由中国玉文化研究会与南京宝缘斋博物馆等主办的大型玉器藏品展览会于日前在南京“七十二坊”举行,有红山文化,良渚文化及元、明、清等各个时期的玉器文物亮相.

　　据介绍,这次参展的古玉藏品共有300多件,来自各国各地的民间收藏佳品,包括红山文化、良渚文化、齐家文化等史前玉器,还有战汉、唐宋、元明清等时代的精品玉器,大多数都是首次在宁展出.其中一对辽金时期的“黄玉春水圆雕”玉器,保存完好,作品展现了当时女真族的生活习俗文化,为金代皇族专用,既是全国孤品,也堪称是此次展会的极品.展会上,还将展出大量现代和田玉、翡翠精品.价值从几百万至数百元不等,由一块整玉雕成“时来运转”玉瓶,价值600多万元,具有很高的欣赏和收藏价值.

　　展会还特邀了全国著名玉器鉴定专家汪遵国和杨培钧为市民现场提供免费鉴定服务.

来源:新浪收藏
分享到： QQ空间 新浪微博 腾讯微博 人人网



TAG:金代玉器孤品水圆雕在南京展出 翡翠 翡翠手镯 feicui 中国翡翠网 翡翠新闻

PV inverter market to resume growth in 2012

PV inverter market to resume growth in 2012

PARIS – The global photovoltaic (PV) inverter market shrank in terms of revenues in 2011 but will return to growth in 2012, exceeding $7 billion, according to IMS Research.

In its annual report, titled "The World Market for PV Inverters", IMS Research said it expects shipments will grow by almost 25 percent. In 2011, global inverter shipments grew by 12 percent, to 27 GW. European inverter market shrank significantly, and its market dominance is expected to continue to wane because Germany and Italy are facing reductions in their annual installations.

In a statement, Ash Sharma, director of the IMS Research PV practice, commented: “In 2012, suppliers will continue to see high shipment growth but may struggle to see top- and bottom-line growth. Inverter prices will see another double-digit drop in 2012, partly driven by product mix change, and shifts in demand to lower cost countries, but also standard price erosion as major markets stagnate.”



TAG:IMS Research Photovoltaics Growth 2012 Market

HiWave tips glasses frames that provide audio

HiWave tips glasses frames that provide audio

LONDON – Next generation headsets and glasses frames will be able to deliver audio in compact way without having to use ear buds or stick things in the ear canal, according to HiWave Technologies plc (Cambridge, England).

The company, which was previously known as NXT and started out as a developer of flat panel speakers, has developed an audio technology that can be integrated in the arms of spectacles and expects it to be taken up in glasses for 3-D gaming and sports and for multimedia headsets.

HiWave is currently demonstrating the Farina platform to potential customers and plans to be able to deliver the components of the audio technology in 4Q12.

The technology is a combination of bending wave transducers and driver electronics. When mounted onto the frames of spectacles, such as those used for 3-D gaming, the so-called Farina transducer stimulates the outer ear, or pinna, with a broadband audio signal, turning the spectacles into headsets. The user then hears via a fusion of airborne sound and soft tissue conduction into the inner ear.

The Farina ceramic vibrating beam measures 25-mm by 3-mm by 0.6-mm and delivers a multi-octave audio frequency range of sound.

A suite of patent grants and applications protects HiWave’s developments in the Farina transducer. These encompass techniques for delivering multi-octave audio from a vibrating beam of miniaturised dimensions, and the methodology for matching the mechanical impedance of ceramic materials to the soft tissues of the human ear.

"Glasses that combine visual and audio input to the user are going to be a huge opportunity for us," said James Lewis, CEO of HiWave, in a statement. He continued: "The goal for our customers will be to create eyewear that incorporates miniaturized display and audio components and are completely wireless. With Farina audio, the mini-transducers will be embedded into the arms of the glasses where they touch the ears and the amplifier circuitry will be a single chip that, together with the Bluetooth or other wireless chip, will disappear into the frame. Our low-power techniques minimize the battery size so that this to can become an integral part of the frame. I believe that technology will open the eyes of product planners, marketing executives and industrial designers to consumer electronics concepts that have never been possible to implement before."


Related links and articles:

www.hi-wave.com

News articles:

Former Movidius executive joins haptic startup as CEO

HiWave embeds haptic response in flat panels

Speaker firm moves into haptic IC design

TAG:HiWave Farina audio driver transducer ceramic 3 D glasses multimedia

PV inverter market to resume growth in 2012

PV inverter market to resume growth in 2012

PARIS – The global photovoltaic (PV) inverter market shrank in terms of revenues in 2011 but will return to growth in 2012, exceeding $7 billion, according to IMS Research.

In its annual report, titled "The World Market for PV Inverters", IMS Research said it expects shipments will grow by almost 25 percent. In 2011, global inverter shipments grew by 12 percent, to 27 GW. European inverter market shrank significantly, and its market dominance is expected to continue to wane because Germany and Italy are facing reductions in their annual installations.

In a statement, Ash Sharma, director of the IMS Research PV practice, commented: “In 2012, suppliers will continue to see high shipment growth but may struggle to see top- and bottom-line growth. Inverter prices will see another double-digit drop in 2012, partly driven by product mix change, and shifts in demand to lower cost countries, but also standard price erosion as major markets stagnate.”



TAG:IMS Research Photovoltaics Growth 2012 Market

HiWave tips glasses frames that provide audio

HiWave tips glasses frames that provide audio

LONDON – Next generation headsets and glasses frames will be able to deliver audio in compact way without having to use ear buds or stick things in the ear canal, according to HiWave Technologies plc (Cambridge, England).

The company, which was previously known as NXT and started out as a developer of flat panel speakers, has developed an audio technology that can be integrated in the arms of spectacles and expects it to be taken up in glasses for 3-D gaming and sports and for multimedia headsets.

HiWave is currently demonstrating the Farina platform to potential customers and plans to be able to deliver the components of the audio technology in 4Q12.

The technology is a combination of bending wave transducers and driver electronics. When mounted onto the frames of spectacles, such as those used for 3-D gaming, the so-called Farina transducer stimulates the outer ear, or pinna, with a broadband audio signal, turning the spectacles into headsets. The user then hears via a fusion of airborne sound and soft tissue conduction into the inner ear.

The Farina ceramic vibrating beam measures 25-mm by 3-mm by 0.6-mm and delivers a multi-octave audio frequency range of sound.

A suite of patent grants and applications protects HiWave’s developments in the Farina transducer. These encompass techniques for delivering multi-octave audio from a vibrating beam of miniaturised dimensions, and the methodology for matching the mechanical impedance of ceramic materials to the soft tissues of the human ear.

"Glasses that combine visual and audio input to the user are going to be a huge opportunity for us," said James Lewis, CEO of HiWave, in a statement. He continued: "The goal for our customers will be to create eyewear that incorporates miniaturized display and audio components and are completely wireless. With Farina audio, the mini-transducers will be embedded into the arms of the glasses where they touch the ears and the amplifier circuitry will be a single chip that, together with the Bluetooth or other wireless chip, will disappear into the frame. Our low-power techniques minimize the battery size so that this to can become an integral part of the frame. I believe that technology will open the eyes of product planners, marketing executives and industrial designers to consumer electronics concepts that have never been possible to implement before."


Related links and articles:

www.hi-wave.com

News articles:

Former Movidius executive joins haptic startup as CEO

HiWave embeds haptic response in flat panels

Speaker firm moves into haptic IC design

TAG:HiWave Farina audio driver transducer ceramic 3 D glasses multimedia

PV inverter market to resume growth in 2012

PV inverter market to resume growth in 2012

PARIS – The global photovoltaic (PV) inverter market shrank in terms of revenues in 2011 but will return to growth in 2012, exceeding $7 billion, according to IMS Research.

In its annual report, titled "The World Market for PV Inverters", IMS Research said it expects shipments will grow by almost 25 percent. In 2011, global inverter shipments grew by 12 percent, to 27 GW. European inverter market shrank significantly, and its market dominance is expected to continue to wane because Germany and Italy are facing reductions in their annual installations.

In a statement, Ash Sharma, director of the IMS Research PV practice, commented: “In 2012, suppliers will continue to see high shipment growth but may struggle to see top- and bottom-line growth. Inverter prices will see another double-digit drop in 2012, partly driven by product mix change, and shifts in demand to lower cost countries, but also standard price erosion as major markets stagnate.”



TAG:IMS Research Photovoltaics Growth 2012 Market

2012年7月和田玉收藏与投资略谈

2012年7月和田玉收藏与投资略谈

　　和田玉,顾名思义,乃中国新疆和田地区所产的玉石.和田古名和阗,这里所谈的和田玉也就是和阗玉,非广义的软玉,或狭义的“玉”.

　　中国和田玉历史悠久,蜚声中外.自古至今,它不仅仅是财富和身份的象征,更是中华民族灿烂文化的重要组成部分.时至今日,人们常说的一些成语和词汇里依然体现着“王玉时代”的语言文化特征,比如“洁白无暇”、“瑕不掩瑜”、“温润而泽”、“君子如玉”、“如花似玉”、“花容玉貌”、“粉妆玉琢”、“亭亭玉立”、“玉树临风”等等,可以说玉文化无处不在……

　　“民玉时代”到来

　　虽说玉文化无处不在,但在封建王朝统治下的中国,普通百姓离真正的“和田玉”距离还是很远.从近几年各大艺术品拍卖行的图录上就可以看出,在明清两代传世的和田玉拍品中,算得上和田玉精品的凤毛麟角、微乎其微.从明清两代的王朝垄断到解放后的外贸独家收购,和田玉矿产资源和艺术品一直是国家统一开采、加工和销售的.随着上世纪80年代中国的改革开放,众多个人和民间团体加入了资源地承包和开采队伍,在苏州、扬州、上海、河南等地也逐渐形成了颇具规模的和田玉加工和销售市场,这也就意味着“王玉时代”的彻底终结,“民玉时代”的到来.各类精美的和田玉作品最终走近千家万户,走进我们的生活……尤其是近些年的艺术品收藏风和投资热,更使得和田玉产品无论是质还是量,都有了一个跨时代的飞跃……

　　“知识”和“价值”

　　说到收藏,就不得不提到两个词——“知识”和“价值”.无论是收藏还是投资,都离不开这两个概念.在掌握了和田玉的基本常识和知识的前提下,才能谈得上对和田玉进行搜罗与收藏.久而久之,随着藏品数量的增加,以藏养藏,以藏贩藏,甚至进行大量资本投入,才能水到渠成、彰显成效.但时下众多的玉文化爱好者和收藏者,多数不具备核心的和田玉知识和收藏理念,甚至有些人在“翠玉不分”、“石玉不分”的状态下迫不及待地加入收藏行列,也就是业内常说的“外行玩家”.这类人群的比例在逐日增加,这类现象也越来越普遍.

　　历史传统的颠覆、教育制度的倾斜、社会文化的变异、浮华逐利的大众心态等是导致这类现象出现的直接或间接的因素……上世纪40、50、60,甚至70年代出生的人,由于受世袭的博古风气和怀旧心态的影响,耳濡目染或多或少地都学习了一些和田玉的常识和知识.无论是懂玉或不懂玉,只要提到“玉”这个字,都不同程度有一种莫名的好感,这就是玉文化的魅力.而80、90后在这种传统文化上则是一个断层,这是社会多元化发展的产物.

　　因此,掌握和田玉知识是每个试图收藏或投资和田玉的人必须下的功夫.而这类知识的积累并非一朝一夕所成,需要海量细致的阅读、科学客观地理解相关书籍,需要频繁地光临和田玉市场和门店,认真冷静地观察和分析和田玉材质、工艺及历史特征,多多听取和田玉经营从业人员的说法和经验,日积月累,才能触类旁通,从众多和田玉真品、赝品和仿品中分辨出真假优劣.因此,笔者对刚入门的爱好者赠送八字真言——“只看不买、多看少买”.学习研究最为关键,这是一个艰辛漫长的过程.只有经过收藏知识的积累,才能了解和田玉真正的价值所在.而和田玉价值的综合比,就如同央视《探索》栏目里所总结的,25%是历史价值,25%是工艺价值,50%是材质价值.众所周知,和田玉从材质上分为两大类——山料和籽料.山料是大块山石开采出来的原生矿料.籽料,是历年昆仑山地质灾害造成的滑坡或洪水冲入玉龙喀什河和喀拉喀什河里的山石,经过几千上万年河水的浸泡和冲刷形成的卵石,又称次生矿料.这种卵石状玉石由于长期的浸泡和石墨的入侵,内外部结构发生了很大的变化,质地坚实,油润光滑,色彩斑斓,成为玉石收藏品中最为独特的宝石.古人言“物以稀为贵”,正因为籽料是在地表和河床里,容易接近,所以自古至今(尤其是近现代)的大量开采,造成和田玉籽料的矿产资源已经彻底枯竭.和田玉的价值体现是完美的,历史文化赋予它深刻的含义,精工细琢成就它外观的超绝,稀缺的资源造就它不菲的身价……

　　玉有“三品”

　　经过长达5000多年的文化积淀,古人早已为我们把艺术收藏品分出了三六九等,业内常说的上三品包括字画、瓷器、玉器.字画瓷器不在本文范畴,姑且不论,玉器也并非单指和田玉.然而,中国四大名玉(新疆和阗玉、辽宁岫岩玉、河南独山玉、陕西蓝田玉)里,新疆和田玉首屈一指.

　　和田玉产品又可细分为三品.第一类为“商品”,也就是所谓的“赝品”,此类“和田玉”材质仿料居多,由最初的俄罗斯料、青海格尔木料、岫岩河磨料发展为现在韩国料、外蒙料、加拿大料等,连玻璃料器也搀杂其中,有些料种甚至说不清产地叫不上名称,造假者无所不用其极.工艺上,以廉价手工和电脑绘图机器雕琢为主,河南南阳市镇平县的石佛寺镇,就是这类和田玉商品的最大集散地.在近几年的和田玉市场上,这类商品的成交量占50%以上,价值从几十上百元到几千元不等,它满足了一般的玉文化爱好者和普通玩家对工艺品甚至是装饰品的需求.

　　第二类“玩品”,也就是圈内人士常说的“正品”.此类和田玉通常都是行家或资深玩家用来收藏和交流的,以和田山料和籽料为主,对于玉料品质、工艺风格、作品题材都比较讲究,也是和田玉经营者最常接触的,价格在几千到几万之间,占整个和田玉市场成交量的30%以上.自新疆原产地和田、乌鲁木齐,到苏州、上海、扬州、蚌埠,此类和田玉比重很大.

　　第三类“藏品”,顾名思义,乃收藏级和田玉作品,也就是所谓的“极品”.材质上追求绝对籽料(偶尔也会有些档次高的俄罗斯料),料种的稀缺和完美程度高.工艺上大多要求是知名大师作品,或是那些虽未成名但手艺了得的匠人所做的精品.这类作品轻易得不到,轻易不示人,轻易不出手,所以价值不菲.值得一提的是,近几年,河南镇平的一些玉匠由于受上海、苏州玉雕风格的影响,工艺水平有了质的飞跃,个别青年玉雕匠人频繁参加国内玉雕大赛并屡屡夺魁,相继涌现出一批国家级玉雕工艺美术大师,他们的作品也较受经营者和资深藏家的追捧.在这里需要强调的是,很多人在学习和田玉收藏知识的过程中容易走入几个误区——“认老不认新”、“认白不认润”、“认皮不认质”、“认工不认料”……这些易让人步入迷途,难以回归初衷,需要注意.言而总之,学习收藏知识必须要找准方向,宁精勿杂,宁缺毋滥.既然是收藏,就要在辨别材质、了解工艺、掌握历史上多下功夫,太过功利往往会得不偿失.

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TAG:2012年7月和田玉收藏与投资略谈 翡翠 翡翠手镯 feicui 中国翡翠网 翡翠新闻

Cadence CEO sees design activity keeping pace

Cadence CEO sees design activity keeping pace

SAN FRANCISCO—Cadence Design Systems Inc. President and CEO Lip-Bu Tan said Wednesday (July 25) he expects to see design activity remain at a good pace in the second half of the year, despite macroeconomic challenges.

Tan's comments came on a conference call with analysts following the company's second quarter financial report, where Cadence reported results that beat analysts' expectations. The company also raised its sales target for the year modestly.

Tan said design activity remained robust in the second quarter, despite macroeconomic challenges such as slowing growth in China, the Eurozone crisis and a slow economic recovery in the U.S. Tan noted that a shortage of 28-nm foundry capacity had cut into sales for some of Cadence's customers and said that both PC shipments and infrastructure equipment sales are showing weakness..

"However, we believe design activity will continue at a good pace in the second half," Tan said. "We are working closely with customers on their most complex designs, our backlog remains strong, and we continue to strengthen our product portfolio. After reviewing our pipeline for the second half, and taking into account the macro risks, we are modestly raising guidance."

Tan said Cadence's 20-nm design technology continues to gain momentum for digital and custom analog chips. Customer engagements for 20-nm are growing in every region, and Cadence is now working with 16 different customers at 20-nm, with more than 30 designs in progress or already complete using the company's Encounter place-and-route tool, Tan said. At the 14-nm node, Cadence has joint projects underway and is working on test chips, he said.

Cadence (San Jose, Calif.) reported second quarter sales of $326 million, up 3 percent from the first quarter and and up 15 percent compared to the second quarter of 2011. The company reported a net income in accordance with generally accepted accounting principles (GAAP) of $36 million, or 13 cents per diluted share, up 16 percent from the first quarter and up 33 percent from the second quarter of 2011.

On a non-GAAP basis, excluding charges, Cadence reported a net income for the second quarter of $53 million, or 19 cents per diluted share, up 13 percent from the first quarter and up 96 percent from the first quarter of 2011.

Cadence's second quarter results bested consensus analysts' expectations, which called for revenue of $321 million and non-GAAP earnings per share of 18 cents, according to Yahoo Finance.

Cadence said it expects third quarter sales to be between $325 million and $335 million, better than consensus analysts' expectations of about $323 million, according to Yahoo Finance. The company expects to report a net income of 17 to 18 cents per share on a GAAP basis, and 18 to 19 cents per share on a non-GAAP basis. Consensus analysts' forecast that the company would guide for non-GAAP earnings per share of 17 cents, according to Yahoo Finance.

For the full year, Cadence expects sales to be between $1.295 billion and $1.315 billion, an increase from the previous forecast, which called for sales of $1.27 billion and $1.3 billion.


TAG:Lip Bu Tan Cadence Design Systems Design Activity

Cadence CEO sees design activity keeping pace

Cadence CEO sees design activity keeping pace

SAN FRANCISCO—Cadence Design Systems Inc. President and CEO Lip-Bu Tan said Wednesday (July 25) he expects to see design activity remain at a good pace in the second half of the year, despite macroeconomic challenges.

Tan's comments came on a conference call with analysts following the company's second quarter financial report, where Cadence reported results that beat analysts' expectations. The company also raised its sales target for the year modestly.

Tan said design activity remained robust in the second quarter, despite macroeconomic challenges such as slowing growth in China, the Eurozone crisis and a slow economic recovery in the U.S. Tan noted that a shortage of 28-nm foundry capacity had cut into sales for some of Cadence's customers and said that both PC shipments and infrastructure equipment sales are showing weakness..

"However, we believe design activity will continue at a good pace in the second half," Tan said. "We are working closely with customers on their most complex designs, our backlog remains strong, and we continue to strengthen our product portfolio. After reviewing our pipeline for the second half, and taking into account the macro risks, we are modestly raising guidance."

Tan said Cadence's 20-nm design technology continues to gain momentum for digital and custom analog chips. Customer engagements for 20-nm are growing in every region, and Cadence is now working with 16 different customers at 20-nm, with more than 30 designs in progress or already complete using the company's Encounter place-and-route tool, Tan said. At the 14-nm node, Cadence has joint projects underway and is working on test chips, he said.

Cadence (San Jose, Calif.) reported second quarter sales of $326 million, up 3 percent from the first quarter and and up 15 percent compared to the second quarter of 2011. The company reported a net income in accordance with generally accepted accounting principles (GAAP) of $36 million, or 13 cents per diluted share, up 16 percent from the first quarter and up 33 percent from the second quarter of 2011.

On a non-GAAP basis, excluding charges, Cadence reported a net income for the second quarter of $53 million, or 19 cents per diluted share, up 13 percent from the first quarter and up 96 percent from the first quarter of 2011.

Cadence's second quarter results bested consensus analysts' expectations, which called for revenue of $321 million and non-GAAP earnings per share of 18 cents, according to Yahoo Finance.

Cadence said it expects third quarter sales to be between $325 million and $335 million, better than consensus analysts' expectations of about $323 million, according to Yahoo Finance. The company expects to report a net income of 17 to 18 cents per share on a GAAP basis, and 18 to 19 cents per share on a non-GAAP basis. Consensus analysts' forecast that the company would guide for non-GAAP earnings per share of 17 cents, according to Yahoo Finance.

For the full year, Cadence expects sales to be between $1.295 billion and $1.315 billion, an increase from the previous forecast, which called for sales of $1.27 billion and $1.3 billion.


TAG:Lip Bu Tan Cadence Design Systems Design Activity

Cadence CEO sees design activity keeping pace

Cadence CEO sees design activity keeping pace

SAN FRANCISCO—Cadence Design Systems Inc. President and CEO Lip-Bu Tan said Wednesday (July 25) he expects to see design activity remain at a good pace in the second half of the year, despite macroeconomic challenges.

Tan's comments came on a conference call with analysts following the company's second quarter financial report, where Cadence reported results that beat analysts' expectations. The company also raised its sales target for the year modestly.

Tan said design activity remained robust in the second quarter, despite macroeconomic challenges such as slowing growth in China, the Eurozone crisis and a slow economic recovery in the U.S. Tan noted that a shortage of 28-nm foundry capacity had cut into sales for some of Cadence's customers and said that both PC shipments and infrastructure equipment sales are showing weakness..

"However, we believe design activity will continue at a good pace in the second half," Tan said. "We are working closely with customers on their most complex designs, our backlog remains strong, and we continue to strengthen our product portfolio. After reviewing our pipeline for the second half, and taking into account the macro risks, we are modestly raising guidance."

Tan said Cadence's 20-nm design technology continues to gain momentum for digital and custom analog chips. Customer engagements for 20-nm are growing in every region, and Cadence is now working with 16 different customers at 20-nm, with more than 30 designs in progress or already complete using the company's Encounter place-and-route tool, Tan said. At the 14-nm node, Cadence has joint projects underway and is working on test chips, he said.

Cadence (San Jose, Calif.) reported second quarter sales of $326 million, up 3 percent from the first quarter and and up 15 percent compared to the second quarter of 2011. The company reported a net income in accordance with generally accepted accounting principles (GAAP) of $36 million, or 13 cents per diluted share, up 16 percent from the first quarter and up 33 percent from the second quarter of 2011.

On a non-GAAP basis, excluding charges, Cadence reported a net income for the second quarter of $53 million, or 19 cents per diluted share, up 13 percent from the first quarter and up 96 percent from the first quarter of 2011.

Cadence's second quarter results bested consensus analysts' expectations, which called for revenue of $321 million and non-GAAP earnings per share of 18 cents, according to Yahoo Finance.

Cadence said it expects third quarter sales to be between $325 million and $335 million, better than consensus analysts' expectations of about $323 million, according to Yahoo Finance. The company expects to report a net income of 17 to 18 cents per share on a GAAP basis, and 18 to 19 cents per share on a non-GAAP basis. Consensus analysts' forecast that the company would guide for non-GAAP earnings per share of 17 cents, according to Yahoo Finance.

For the full year, Cadence expects sales to be between $1.295 billion and $1.315 billion, an increase from the previous forecast, which called for sales of $1.27 billion and $1.3 billion.


TAG:Lip Bu Tan Cadence Design Systems Design Activity

NASA preps spacecraft for risky Mars landing attempt

NASA preps spacecraft for risky Mars landing attempt

WASHINGTON – NASA said this week it has repositioned its orbiting Mars Odyssey spacecraft so it can more quickly relay the results of a harrowing landing attempt next month by a spacecraft carrying the Curiosity rover.

Separately, NASA officials declined to estimate the odds for a successful landing next month.

Just before the attempt to land the Mars Science Laboratory carrying Curiosity on Aug. 6, mission managers said Earth will be positioned below the Martian horizon as the spacecraft descends toward its landing site near Gale Crater. While the spacecraft can send limited data as it approaches the thin Martian atmosphere, the repositioned Odyssey spacecraft that has been orbiting Mars since 2001 is now in a better position to relay confirmation of a landing back to NASA controllers at the Jet Propulsion Laboratory (JPL, Pasadena, Calif.).

Without the repositioning maneuver on Tuesday (July 24), NASA officials said Odyssey would have arrived over Curiosity’s landing site about two minutes after a sky crane tries to lower it to the surface. A six second thruster burn moved Odyssey about six minutes ahead to align its orbital pass with the planned landing site.

Mission managers previously reported that Odyssey had unexpectedly entered a “safe mode” on July 11, raising concerns about how long it would take to receive confirmation of a landing. The issue has since been resolved, and NASA said “Odyssey is now operating normally.”

Confirmation of Curiosity’s scheduled landing on Mars is expected to reach Earth at 1:31 a.m. eastern time on Aug. 6.
Two other spacecraft – NASA’s Mars Reconnaissance Orbiter and the European Space Agency’s Mars Express – will record radio transmission for later playback. Only Odyssey will be in a position to relay information in near real time, NASA said.

In preparation for the risky landing attempt that marks the first time a sky crane will be used to lower the SUV-sized rover to the surface, mission managers also said they had completed a week-long process of rebooting and configuring the spacecraft’s two redundant main computers. The uplink included spacecraft configuration parameters for entering the Martian atmosphere, descent, landing and surface operations.

Earlier this week, engineers began configuring Curiosity’s navigation system in advance of the landing attempt. That step involved configuration of two inertial measurement units on the spacecraft’s descent stage.

Given the unprecedented size and weight of the Curiosity rover, NASA engineers were forced to come up with a risky sky crane technique to land on Mars. Onboard computers will be required to automatically execute a series of complex commands during the approximately seven minutes it will take for the spacecraft carrying Curiosity to descend through the atmosphere to the Martian surface.

Ask if mission planners had calculated the chances for success, JPL spokesman Guy Webster replied: “No. Important risks are the unknowns, which resist calculating.”

Related story:

Video: '7 minutes of terror' for next Mars probe
TAG:Mars Science Laboratory Mars Odyssey Spacecraft Mars Landing Curiosity Rover NASA Curiosity Mars

NASA preps spacecraft for risky Mars landing attempt

NASA preps spacecraft for risky Mars landing attempt

WASHINGTON – NASA said this week it has repositioned its orbiting Mars Odyssey spacecraft so it can more quickly relay the results of a harrowing landing attempt next month by a spacecraft carrying the Curiosity rover.

Separately, NASA officials declined to estimate the odds for a successful landing next month.

Just before the attempt to land the Mars Science Laboratory carrying Curiosity on Aug. 6, mission managers said Earth will be positioned below the Martian horizon as the spacecraft descends toward its landing site near Gale Crater. While the spacecraft can send limited data as it approaches the thin Martian atmosphere, the repositioned Odyssey spacecraft that has been orbiting Mars since 2001 is now in a better position to relay confirmation of a landing back to NASA controllers at the Jet Propulsion Laboratory (JPL, Pasadena, Calif.).

Without the repositioning maneuver on Tuesday (July 24), NASA officials said Odyssey would have arrived over Curiosity’s landing site about two minutes after a sky crane tries to lower it to the surface. A six second thruster burn moved Odyssey about six minutes ahead to align its orbital pass with the planned landing site.

Mission managers previously reported that Odyssey had unexpectedly entered a “safe mode” on July 11, raising concerns about how long it would take to receive confirmation of a landing. The issue has since been resolved, and NASA said “Odyssey is now operating normally.”

Confirmation of Curiosity’s scheduled landing on Mars is expected to reach Earth at 1:31 a.m. eastern time on Aug. 6.
Two other spacecraft – NASA’s Mars Reconnaissance Orbiter and the European Space Agency’s Mars Express – will record radio transmission for later playback. Only Odyssey will be in a position to relay information in near real time, NASA said.

In preparation for the risky landing attempt that marks the first time a sky crane will be used to lower the SUV-sized rover to the surface, mission managers also said they had completed a week-long process of rebooting and configuring the spacecraft’s two redundant main computers. The uplink included spacecraft configuration parameters for entering the Martian atmosphere, descent, landing and surface operations.

Earlier this week, engineers began configuring Curiosity’s navigation system in advance of the landing attempt. That step involved configuration of two inertial measurement units on the spacecraft’s descent stage.

Given the unprecedented size and weight of the Curiosity rover, NASA engineers were forced to come up with a risky sky crane technique to land on Mars. Onboard computers will be required to automatically execute a series of complex commands during the approximately seven minutes it will take for the spacecraft carrying Curiosity to descend through the atmosphere to the Martian surface.

Ask if mission planners had calculated the chances for success, JPL spokesman Guy Webster replied: “No. Important risks are the unknowns, which resist calculating.”

Related story:

Video: '7 minutes of terror' for next Mars probe
TAG:Mars Science Laboratory Mars Odyssey Spacecraft Mars Landing Curiosity Rover NASA Curiosity Mars